In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

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In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. The combinational ATPG method allows testing the individual nodes or flip-flops of the logic circuit without being concerned with the operation of the overall circuit. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault.

Automatic test pattern generation – Wikipedia

If one driver dominates the other driver in a bridging situation, the dominant driver forces the logic to the other one, in such case a dominant basic fault is used. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Bridging to VDD or Vss is equivalent to stuck at fault model. In such a circuit, any single fault will be inherently undetectable.

These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns. At transistor level, a transistor maybe stuck-short or stuck-open.

For nanometer technology, many current design validation problems are becoming manufacturing test problems as well, so new fault-modeling and ATPG techniques will be needed. A fault model is a mathematical description of how a defect alters design behavior.

Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences.

In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity. However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs. For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.


Equivalent faults produce the same faulty behavior for all input patterns. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. This model is used to describe faults for CMOS logic gates.

This allows using a relatively simple vector matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs. The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. By using this site, you agree to the Terms of Use and Privacy Policy.

Combinational ATPG Basics

Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Various search strategies and heuristics have been devised to find a shorter sequence, or to find a sequence faster. The effectiveness of ATPG is measured by the number of modeled defects, or fault modelsdetectable and by the number of generated bxsics.

However, according arpg reported results, no single strategy or heuristic out-performs others for all applications or circuits. Fault activation establishes a signal value at the fault model site that is opposite of the value produced by the fault model. A short circuit between two signal lines is called bridging faults.

The logic values observed at the device’s primary outputs, while applying a test pattern to some device under test DUTare called the output of that test pattern. The classic example of this is a redundant circuit, designed such that no single fault causes the output to change.

ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of abstraction used to represent the circuit under test gate, register-transfer, switch nasics, and the required test quality.

In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off. During test, a so-called scan-mode is enabled forcing all flip-flops FFs to be connected in a simplified fashion, effectively bypassing their interconnections as intended during normal operation. The single stuck-at fault model is structural because it is defined based on a structural gate-level circuit model. From Wikipedia, the free encyclopedia.

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Any single fault from the set of equivalent faults can represent the whole set. It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.

Second, it is possible that a detection pattern exists, but the algorithm cannot find one. Historically, ATPG has focused on a set of faults derived atpgg a gate-level fault model. Basiccs fault modeling and vector-generation techniques are giving way to new models and techniques that consider timing information during test generation, that are scalable to larger designs, basicz that can capture extreme design conditions.

This page was last edited on 23 Novemberat Therefore, many different ATPG methods have been developed to address combinational and sequential circuits. ATPG can fail to find a test for a particular fault in at least two cases. In the latter case, dominant driver keeps its value, while the other one gets the AND or OR value of its own and the dominant driver. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

Automatic test pattern generation

The ATPG process for a targeted fault consists of two phases: This bqsics implies that a test generator should include a comprehensive set of heuristics. As design trends move toward nanometer technology, new manufacture testing problems are emerging. The generated patterns are used to test semiconductor devices atog manufacture, or to assist with determining the cause of failure failure analysis [1].

Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, of which some can be viewed as being equivalent to others.