LXTALE from Intel Corporation. Find the PDF Datasheet, Specifications and Distributor Information. (This Datasheet also supports the LXT PHY.) Applications. Product Features LXTALE – Extended (° to 85 °C amb.) ▫ LXTALC. LXTALE Networking & Communications – Ethernet Products – Ethernet PHYs/ Macs/transceivers Details, datasheet, quote on part number: LXTALE.
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August 7, 65 LXTA 3. The scrambler is automatically bypassed when the fiber port is enabled.
The LED changes state blinks when a collision occurs. August 7, 45 LXTA 3. It is always generated when a packet is received from the line and in half-duplex mode when a packet is transmitted. When the network link is forced to a specific configuration, the LXTA immediately begins operating the network interface as commanded. Not guaranteed or production tested. During 10 Mbps operation, Manchester-encoded data is exchanged.
This feature is provided as a diagnostic tool. August 7, 57 LXTA 3. The LXTA transmits the far-end fault code a minimum of three times if all the following conditions are true: These display settings are stretched regardless of the value of The LXTA automatically exits jabber mode after the unjabber time has expired.
August 7, 51 LXTA 3. Test clock input sourced by ATE. Fiber mode is selected through Register bit Parameter is guaranteed by design; not subject to production testing. August 7, 63 LXTA pxt971ale. Fault Code transmission is enabled Register bit The hardware option uses the three LED driver pins. Test data driven with respect to the falling edge of TCK. During full-duplex operation Register bit 0. August 7, 85 LXTA 3. Both sides must receive at least three identical base pages for negotiation to continue.
Designers must not rely pxt971ale the absence or characteristics of any features or instructions marked “reserved” or “undefined. Normal Operation TP Mode: Furthermore, Mbps idle patterns will not bring up a 10 Mbps link.
If Register bit August 7, 35 LXTA 3. Intel recommends that all inputs and multi-function pins be tied to the dataasheet states and all outputs be left floating, if unused. Operational loopback is not provided for Mbps links, full-duplex links, or when Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel’s website at http: Refer to Figure 3 on page 13 for specific pin assignments.
This allows the designer to optimize the output waveform to match the characteristics of the magnetics. A High Lxt917ale High impedance or three-state determines when the device is drawing a current lxf971ale less than 20 nA. They revert back to the values that were read in during the last hardware reset. RO hex 1.
Interrupt logic is shown in Figure 6. This bit is only valid when auto negotiate is enabled, and is equivalent to Register bit 1. In this mode the power consumption is minimized, and the supply current is reduced below the maximum value given in Table 18 on page datsheet Control Register Address 0 Bit Name 0.
LXTALE Datasheet(PDF) – Intel Corporation
When the stretch timer expires the edge detector is reset so that a long event causes another pulse to be generated from the edge detector which resets the stretch timer and causes the LED driver to remain asserted.
Test reset input sourced by ATE. A separate ferrite bead rated at 50 mA should be used to supply center-tap current. Default value of Register bits 0. The LXTA may contain design defects or errors known as errata which may cause the product to deviate from published specifications. August 7, 61 LXTA 3. The LED driver remains asserted until the stretch timer expires. On the transmit side, the LXTA has an active internal termination and does not require external termination resistors.
Additional power savings may be realized by supplying the center-tap from a 2.
All weak pad pull-up and pull-down resistors are disabled.